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LP621024D-I Series
Preliminary
Document Title 128K X 8 BIT CMOS SRAM Revision History
Rev. No.
0.0
128K X 8 BIT CMOS SRAM
History
Initial issue
Issue Date
August 9, 2002
Remark
Preliminary
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Preliminary
Features
n Single +5V power supply n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 70mA (max.) Standby: 50A (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin DIP, SOP TSOP and TSSOP (8 X 13.4mm) packages
128K X 8 BIT CMOS SRAM
General Description
The LP621024D-I is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V.
Product Family
Product Family Operating Temperature VCC Range Power Dissipation Speed Data Retention (ICCDR, Typ.) 0.5A Standby (ISB1, Typ.) 2A Operating (ICC2, Typ.) 10mA Package Type 32L DIP/ SOP/TSOP/ TSSOP
LP62S1024D
-40C ~ +85C
4.5V~5.5V
55ns / 70ns
1. Typical values are measured at VCC = 5.0V, TA = 25C and not 100% tested. 2. Data retention current VCC = 2.0V.
Pin Configurations
n DIP
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND
n SOP
1 2 3 4 5 32 31 30 29 28 VCC A15 CE2 WE A13
n TSOP/(TSSOP)
16
1
LP621024DM-I
LP621024DV-I (LP621024DX-I)
6 7 8 9 10 11 12 13 14 15 16
27 26 25 24 23 22 21 20 19 18 17
A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 17
PRELIMINARY
LP621024D-I
32
Pin No. Pin Name Pin No. Pin Name
1 A11 17 A3
2 A9 18 A2
3 A8 19 A1
4 A13 20 A0
5 WE 21 I/O1
6 CE2 22 I/O2
7 A15 23 I/O3
8 VCC 24 GND
9 NC 25 I/O4
10 A16 26 I/O5
11 A14 27 I/O6
12 A12 28 I/O7
13 A7 29 I/O8
14 A6 30 CE1
15 A5 31 A10
16 A4 32 OE
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Block Diagram
A0 VCC GND A14 A15 A16 ROW DECODER 512 X 2048 MEMORY ARRAY
I/O1
INPUT DATA CIRCUIT
COLUMN I/O
I/O8
CE2 CE1 OE WE
CONTROL CIRCUIT
Pin Descriptions - DIP/SOP
Pin No. 1 2 - 12, 23, 25 - 28, 31 13 - 15, 17 - 21 16 22 24 29 30 32 Symbol NC A0 - A16 Description No Connection Address Inputs
Pin Description - TSOP/TSSOP
Pin No. 1 - 4, 7, 10 - 20, 31 5 6 8 9 21 - 23, 25 - 29 24 30 32 Symbol A0 - A16 WE CE2 VCC NC I/O1 - I/O8 GND CE1 OE Description Address Inputs Write Enable Chip Enable Power Supply No Connection Data Input/Outputs Ground Chip Enable Output Enable
I/O1 - I/O8 GND CE1 OE WE CE2 VCC
Data Input/Outputs Ground Chip Enable Output Enable Write Enable Chip Enable Power Supply (+5V)
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Recommended DC Operating Conditions
(TA = -40C to + 85C) Symbol Parameter Supply Voltage GND VIH VIL CL TTL Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 4.5 0 2.2 -0.3 Typ. 5.0 0 3.5 0 Max. 5.5 0 VCC + 0.3 +0.8 30 1 Unit V V V V pF -
Absolute Maximum Ratings*
VCC to GND ............................................. -0.5V to + 7.0V IN, IN/OUT Volt to GND ....................-0.5V to VCC + 0.5V Operating Temperature, Topr .................. -40C to + 85C Storage Temperature, Tstg.................... -55C to + 125C Temperature Under Bias, Tbias............... -10C to + 85C Power Dissipation, PT ....................................................................... 0.7W Soldering Temp. & Time .............................260C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol Parameter
(TA = -40C to + 85C, VCC = 5V 10%, GND = 0V) LP621024D-55LLI Min. Max. 1 LP621024D-70LLI Min. Max. 1 A VIN = GND to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC CE1 = VIL, CE2 = VIH II/O = 0mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1MHZ, II/O = 0mA Unit Conditions
ILI
Input Leakage Current
-
ILO
Output Leakage Current Active Power Supply Current
-
1
-
1
A
ICC
-
15
-
15
mA
ICC1
Dynamic Operating Current
-
70
-
70
mA
ICC2
-
15
-
15
mA
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
DC Electrical Characteristics (continued)
Symbol Parameter LP621024D-55LLI Min. ISB Max. 2 LP621024D-70LLI Min. Max. 2 mA CE1 = VIH or CE2 =VIL CE1 VCC - 0.2V CE2 VCC - 0.2V VIN 0V CE2 0.2V VIN 0V IOL = 2.1mA Unit Conditions
ISB1
Standby Power Supply Current
-
50
-
50
A
ISB2 Output Low Voltage Output High Voltage
-
50
-
50
A
VOL
-
0.4
-
0.4
V
VOH
2.4
-
2.4
-
V
IOH = -1.0mA
Truth Table
Mode Standby CE1 H X Output Disable Read Write Note: X = H or L L L L CE2 X L H H H OE X X H L X WE X X H H L I/O Operation High Z High Z High Z DOUT DIN Supply Current ISB, ISB1 ISB, ISB2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2
Capacitance (TA = 25C, f = 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 6 8 Unit pF pF Conditions VIN = 0V VI/O = 0V
* These parameters are sampled and not 100% tested.
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AMIC Technology, Inc.
LP621024D-I Series
AC Characteristics (TA = -40C to + 85C, VCC = 5V 10%)
Symbol Parameter LP621024D-55LLI Min. Read Cycle tRC tAA tACE1 tACE2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 55 50 0 50 40 0 0 25 0 5 25 70 60 0 60 50 0 0 30 0 5 30 ns ns ns ns ns ns ns ns ns ns Output Disable to Output in High Z Output Hold from Address Change Output Enable to Output in Low Z Chip Disable to Output in High Z CE1 CE2 Output Enable to Output Valid Chip Enable to Output in Low Z CE1 CE2 Read Cycle Time Address Access Time Chip Enable Access Time CE1 CE2 55 10 10 5 0 0 0 5 55 55 55 30 20 20 20 70 10 10 5 0 0 0 5 70 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns Max. LP621024D-70LLI Min. Max. Unit
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Timing Waveforms
Read Cycle 1
(1, 2, 4)
tRC Address
tAA tOH tOH
DOUT
Read Cycle 2
(1, 3, 4, 6)
CE1
tACE1 tCLZ15
tCHZ15
DOUT
Read Cycle 3
(1, 4, 7, 8)
CE2
tACE2 tCLZ25 tCHZ25
DOUT
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Timing Waveforms (continued)
Read Cycle 4
(1)
tRC Address tAA
OE
tOE tOLZ5
tOH
CE1
tACE1 tCLZ15 CE2 tACE2 tCLZ2 DOUT
5
tCHZ15
tOHZ 5 tCHZ25
Notes: 1. 2. 3. 4. 5. 6. 7. 8.
WE is high for Read Cycle. Device is continuously enabled CE1 = VIL and CE2 = VIH. Address valid prior to or coincident with CE1 transition low. OE = VIL. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested. CE2 is high. CE1 is low. Address valid prior to or coincident with CE2 transition high.
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Timing Waveforms (continued)
Write Cycle 1 (Write Enable Controlled)
(6)
tWC Address tAW tCW CE1 (4)
5
tWR3
CE2
(4) tAS1 tWP2
WE
tDW
tDH
DIN tWHZ tOW DOUT
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AMIC Technology, Inc.
LP621024D-I Series
Timing Waveforms (continued)
Write Cycle 2 (Chip Enable Controlled)
tWC Address tAW tCW5 CE1 tAS1 (4) tWR3
CE2
(4) tCW5 tWP2
WE
tDW DIN
tDH
tWHZ7
DOUT
Notes: 1. 2. 3. 4.
tAS is measured from the address valid to the beginning of Write. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE . tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
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AMIC Technology, Inc.
LP621024D-I Series
AC Test Conditions
Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 5 ns 1.5V See Figures 1 and 2
+5V 1800 I/O I/O
+5V 1800
990
30pF*
990
5pF*
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = -40C to 85C)
Symbol VDR1 VDR2 VCC for Data Retention Parameter Min. 2.0 2.0 Max. 5.5 5.5 Unit V V Conditions CE1 VCC - 0.2V CE2 0.2V CE1 VCC - 0.2V or CE1 0.2V VCC = 2.0V, CE1 VCC - 0.2V CE2 VCC - 0.2V VIN 0V VCC = 2.0V CE2 0.2V VIN 0V See Retention Waveform
ICCDR1 Data Retention Current ICCDR2
LL-Version
-
20**
A
LL-Version
-
20**
A ns ms
tCDR tR
Chip Disable to Data Retention Time Operation Recovery Time ICCDR: Max.
0 5
-
** LP621024D-55LLI/70LLI
2A at TA = 0C to + 40 C
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE VCC 4.5V tCDR VDR 2V 4.5V tR
CE1
VIH CE1 VDR - 0.2V
VIH
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE VCC 4.5V tCDR VDR 2V 4.5V tR
CE2
VIL CE2 < 0.2V
VIL
PRELIMINARY
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AMIC Technology, Inc.
LP621024D-I Series
Ordering Information
Part No. LP621024D-55LLI LP621024DM-55LLI LP621024DV-55LLI LP621024DX-55LLI LP621024D-70LLI LP621024DM-70LLI LP621024DV-70LLI LP621024DX-70LLI 70 55 Access Time (ns) Operating Current Max. (mA) 70 70 70 70 70 70 70 70 Standby Current Max. (A) 50 50 50 50 50 50 50 50 Package 32L DIP 32L SOP 32L TSOP 32L TSSOP 32L DIP 32L SOP 32L TSOP 32L TSSOP
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AMIC Technology, Inc.
LP621024D-I Series
Package Information P-DIP 32L Outline Dimensions
unit: inches/mm
D 32 17
E1
1 S
16 E C
A2
A
A1
Base Plane
Seating Plane B B1 e1 eA
L
Symbol A A1 A2 B B1 C D E E1 e1 L eA S
Dimensions in inches 0.210 Max. 0.010 Min. 0.1550.010 0.018 +0.004 -0.002 0.050 +0.004 -0.002 0.010 +0.004 -0.002 1.650 Typ. (1.670 Max.) 0.6000.010 0.550 Typ. (0.562 Max.) 0.1000.010 0.1300.010 0 ~ 15 0.6550.035 0.090 Max.
Dimensions in mm 5.33 Max. 0.25 Min. 3.940.25 0.46 +0.10 -0.05 1.27 +0.10 -0.05 0.25 +0.11 -0.05 41.91 Typ. (42.42 Max.) 15.240.25 13.97 Typ. (14.27 Max.) 2.540.25 3.300.25 0 ~ 15 16.640.89 2.29 Max.
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
PRELIMINARY
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AMIC Technology, Inc.
LP621024D-I Series
Package Information SOP (W.B.) 32L Outline Dimensions
32 17 e1 ~ ~
unit: inches/mm
HE
E
L 1 b 16
Detail F
e1 c A2 A
D
s Seating Plane y D
e
A1
LE See Detail F
Symbol A A1 A2 b c D E e e1 HE L LE S y
Dimensions in inches 0.118 Max. 0.004 Min. 0.1060.005 0.016 +0.004 -0.002 0.008 +0.004 -0.002 0.805 Typ. (0.820 Max.) 0.4450.010 0.050 0.006 0.525 NOM. 0.5560.010 0.0310.008 0.0550.008 0.044 Max. 0.004 Max. 0 ~ 10
Dimensions in mm 3.00 Max. 0.10 Min. 2.690.13 0.41 +0.10 -0.05 0.20 +0.10 -0.05 20.45 Typ. (20.83 Max.) 11.300.25 1.270.15 13.34 NOM. 14.120.25 0.790.20 1.400.20 1.12 Max. 0.10 Max. 0 ~ 10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Package Information TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
D
unit: inches/mm
e
A2
12.0 c A
GAUGE PLANE
E
A1
0.25 BSC
L LE
HD Detail "A" Detail "A"
y
D
S
b
0.10(0.004)
M
Symbol A A1 A2 b c D E e HD L LE S Y
Dimensions in inches 0.047 Max. 0.0040.002 0.0390.002 0.0080.001 0.0060.001 0.7240.004 0.3150.004 0.020 TYP. 0.7870.007 0.0200.004 0.031 TYP. 0.0167 TYP. 0.004 Max. 0 ~ 6
Dimensions in mm 1.20 Max. 0.100.05 1.000.05 0.200.03 0.150.02 18.400.10 8.000.10 0.50 TYP. 20.000.20 0.500.10 0.80 TYP. 0.425 TYP. 0.10 Max. 0 ~ 6
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.
LP621024D-I Series
Package Information TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
e
12.0 A2 E c A
GAUGE PLANE
A1
0.25 BSC
L LE
D1 D Detail "A"
Detail "A"
D
0.10MM
S
SEATING PLANE
b
Symbol A A1 A2 b c E e D D1 L LE S y
Dimensions in inches 0.049 Max. 0.002 Min. 0.0390.002 0.0080.001 0.0060.0003 0.3150.004 0.020 TYP. 0.5280.008 0.4650.004 0.020.008 0.0266 Min. 0.0109 TYP. 0.004 Max. 0 ~ 6
Dimensions in mm 1.25 Max. 0.05 Min. 1.000.05 0.200.03 0.150.008 8.000.10 0.50 TYP. 13.400.20 11.800.10 0.500.20 0.675 Min. 0.278 TYP. 0.10 Max. 0 ~ 6
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
PRELIMINARY
(August, 2002, Version 0.0)
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AMIC Technology, Inc.

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